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    Abstract: A 256-bit adder
is designed using 22-nm strained CMOS Technology which are attractive for
future VLSI and ULSI application. Carry skip adders (CSKA) are widely used in
cascaded circuit connection and it also improves the delay of the circuit
compared to other adders. In this paper, the performance and an analysis on the
delay, power, space and speed of strained CMOS technology based static carry
skip adder will be presented. The circuits are simulated using 22-nm high
performance CMOS with a low supply voltage of 0.8V using HSPICE software tool.
The performance of the adder circuit is analyzed by measuring the key parameters
of the circuit such as speed, power and also the effect of temperature on
circuit performance is also analyzed.

Keywords- CMOS
technology, Carry Skip Adder, high performance, low power supply

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                          I.  INTRODUCTION

HIGH-Speed Adders are
configured according to desired complexity of arithmetic and numeric
computation. High Speed adders are used in the arithmetic logic units and are
also utilized in other parts of the processor, where they are used to calculate
addresses, table indices, increment and decrement operators. Carry Skip Adder
technique is based on the detection and by-passing of those stages of a binary
adder during addition there exist the condition for carry propagation 1. Delay
estimation of designs was initially based on the number of logic levels. Low
power designs have often been compared based on area or total gate count.
However, gate count does not account for the impact of transistors sizing and
supply voltage scaling energy and delay 2. In a well designed circuit, large area
usually means more complicated circuits, which means more transistors or
interconnects or both. This implies a higher load capacitance, hence more power
dissipation. A uniform static CMOS layout strategy is used for all adders,
whereby the short circuit power consumption is minimized 3. The performance
of the circuit will be degraded dramatically or become non-operative at low
supply
voltage.
In CMOS process technology, a systematic and effective way of sizing the
transistors for optimal performance is necessary. As Moore’s law continues to
provide designers with more transistors on a chip, power budgets are beginning
to limit the applicability of these additional circuits in conventional CMOS
design. The design of CSA requires a straight forward optimization technique
that provides an insight into adder delay dependence on gate delay and
number of bits, possibly in analytical way 4-6. The algorithm for
Carry-Skip adder is mentioned from one level skip algorithm to multiple levels
7. In VLSI applications, area and power are important factors which must be
taken into account in the design of a fast adder. Some general rules have been
generated for its design, but they tend to overlook many important implementation
details with different delays in carry path. Numerous power management
techniques targeting
different components of
power have been proposed 8-10. The critical delay of the circuit with two
stage function speculation can be reduced as much as half of the original
delay. The long latency path and short latency path that determine supply
voltage scaling. The long latency path is shown with bold lines and the short
latency path is shown with dashed line 11-12. Further concept of the paper are
organized as follows. An overview of the Structure of Static Carry Skip Adder
in Section II. The Simulation results are given in Section III. Section IV
summarizes the work.                  

II. STRUCTURE OF STATIC CARRY SKIP   ADDER

Carry Skip Adder
improves the delay of the circuit compared to other adder circuits. The worst
case delay is achieved by using several carry skip adders to form a block of
carry skip adder. This adder is an efficient one according to its area usage
and power consumption. A carry skip adder is also known as   carry-by
pass adder. The most widely used techno

-logy is CMOS
logic due to the advantages like low power consumption with no static power
performance. A Static CMOS technology are implemented by using combination of
two networks, the Pull-up network (PUN) and Pull-down network (PDN). The Speed
of the static CMOS circuit depends on the transistor sizing. The problem of
implementing this is more area required to implement the logic i.e., 2N number
of transistors are required. In this, a 256-bit adder is designed using 22-nm
strained silicon CMOS technology and it uses the supply voltage 0.8V. The Carry
Skip Adder is designed with Static CMOS technology so that it will require more
number of transistors.

  A.
CONVENTIONAL CARRY SKIP ADDER   

The Structure of the
Conventional Carry Skip Adder is shown in Fig. 1. The Conventional Carry Skip
Adder consists of four block of Full Adders (Ripple Carry Adder block), four
two input EX-OR gates, Single four input AND gate and Single 2:1 Multiplexer.
Here four-bit Conventional Carry Skip Adder (CSKA) is designed using Static
CMOS Technology. To design a Single bit Full Adder 46 transistors are needed.
For designing four-bit Carry Skip Adder (CSKA) four blocks of Full Adder is
required. Totally 246 transistors are needed to design Conventional Carry Skip
Adder. The Carry Skip Adder is an efficient adder with power consumption

   Fig. 1:
Schematic Diagram of Conventional Carry Skip Adder 18  

and area usage.
The function of Ripple Carry Adder is given as multiple full adder circuits can
be cascaded in parallel to add an N-bit number. For an N-bit parallel adder,
there must be N number of full adder circuits. A ripple Carry Adder (RCA) is a
logic circuit in which the carry-out of each full adder is the carry-in of the
succeeding next most significant full adder. It is called ripple carry adder
because each carry bit gets rippled into the next stage. Totally 184 transistors are
needed to design four block of ripple carry adder. The function of EX-OR gate
is if both the input are low or if both the input are high, the output will be
zero. Otherwise the output will be high. Likewise it perform the operation and
produces the output Y0, Y1, Y2, Y3. These output will be given as input to the
AND gate and it produces the output P0 (P0=Y1Y2Y3Y4).  Then P0 will be the select line of 2:1 MUX.
The Ripple Carry Adder block output Carry C3 and input C in are the inputs of 2:1MUX
and it produces the output C out. The value of C out can be calculated by

                           

     If the P0 value is one directly C in is
given as input to 2:1 MUX. If the P0 value is zero then it perform the
operation of Ripple Carry Adder block and its carry C3 is given as input to 2:1
MUX from that the output is calculated.

B. PROPOSED CARRY SKIP ADDER                                    

  

Fig. 2: Schematic Diagram of Proposed  Carry Skip Adder 18   

The Structure of
proposed Carry Skip Adder is shown in Fig. 2. The Proposed Carry Skip Adder
consists of consists of  input bits from
A0-A7 , B0-B7 and C in. The Proposed 8-bit Carry Skip Adder is designed using
22nm Strained silicon Static CMOS technology. For a single bit adder 46
transistor are needed. For a 8-bit 8- bit adder 368 are needed. Totally 460
transistors are needed to design Proposed 8- bit Carry Skip Adder. So that it
require more number of transistors and it occupies more space. Delay will occur
while performing the function. The function of 
Proposed Carry Skip Adder is each stages consists of two input  bits A and B and RCA block. The first
stage  perform the operation and produces
the output sum and carry where the carry of first block is given as C in  to the next stage. Simultaneously compute for
all stages. In this first block consists of 
one block (RCA) and other blocks consists of  RCA block and incrementation  block. The internal structure of incrementation
block is shown in Fig. 3 which consists a chain of half adders. In Conventional
CSKA the skip logic is not able to bypass the zero carry input until the zero
carry input propagates from the corresponding RCA block. To solve this problem,
the Proposed CSKA is designed. In this, the 
RCA
block
with carry input of zero is used. The RCA block of the stage does not need to
wait for carry output of the previous stage, the output carries of the blocks
are calculated in parallel.

Fig. 3: Schematic Diagram of Proposed Carry

                        Skip Adder 18

                III. SIMULATION RESULTS

The Simulation results
using HSPICE Software tool in high performance and low power 22nm Strained
Silicon CMOS technology at a temperature of 107 (0C) for
4-bit Conventional Static CSKA and 8-bit Proposed CSKA and the supply voltage
used in the simulation is 0.8V. The input Waveform of 4-bit Conventional Static
CSKA is shown in Fig. 4. The Output Waveform of 4-bit Conventional Static CSKA
is shown in Fig. 5. The input Waveform of 8- bit Proposed Static CSKA is shown
in Fig. 6. The Output Waveform of 8-bit Proposed Static CSKA is shown in Fig.
7.The effect of temperature for the 4-bit Conventional Static CSKA is shown in
Fig. 8. The effect of temperature for the 8-bit Proposed CSKA is shown in Fig.
9.The effect of temperature characteristics of Static Carry Skip Adder sweeps
from 27 (0C) to 107 (0C).
From Fig. 8 it is found that when the temperature is 27 (0C), the
delay is 82ps and the power obtained is 54 microwatt. When the temperature is
107 (0C), the delay is 101.4ps and the power obtained is 45.3
microwatt. From Fig. 9 it is found that when the temperature is 27 (0C),
the delay is 104ps and the power obtained is 104 microwatt. When the
temperature is 107 (0C), the delay is 136ps and the power obtained
is 87.2 microwatt. It Shown that as the temperature increases the delay of the
circuit also increases due to the reduction in actual power.

         
Fig.
4: Input Waveform of 4-bit Conventional Static Carry          Skip Adder

       
 Fig. 5: Output Waveform of 4-bit Conventional
Static Carry Skip Adder

    
     Fig. 6: Input Waveform of
8-bit Proposed Static Carry Skip Adder

     
Fig. 7: Output Waveform of 8-bit Proposed Static Carry Skip Adder

  Fig. 8: Delay Vs Temperature Characteristics
of   Conventional       Static Carry Skip Adder Using 22nm CMOS
technology 

 Fig.  9:
Delay Vs Temperature Characteristics of Conventional   Static Carry Skip Adder Using 22nm CMOS
technology  

     

Fig. 10: Delay Vs
Temperature Characteristics of Proposed Static Carry Skip Adder Using 22nm CMOS
technology    

  

Fig. 11: Power Vs
Temperature Characteristics of Proposed Static Carry Skip Adder Using 22nm CMOS
technology

Table I Compares
the Performance of the above mentioned Static Carry Skip Adder

                                            TABLE-1

PERFORMANCE OF THE STATIC CARRY SKIP
ADDER USING  22nm STRAINED SILICON CMOS
TECHNOLOGY

ADDER TYPE

STATIC
CONVENTIONAL  ADDER

STATIC  PROPOSED ADDER

 

DELAY
(ps)

POWER
(microwatt)

DELAY
(ps)

POWER
(microwatt)

4BIT ADDER

101.4

45.3

     –

       –

8BIT ADDER

202.8

90.6

208

174.4

16BIT ADDER

405.6

181.2

416

348.8

32BIT ADDER

811.2

362.4

832

697.6

64BIT ADDER

1622.4

724.8

1664

1395.2

28BIT ADDER

3244.8

1449.6

3328

2790.4

256BIT ADDER

6489.6

2899.2

6656

5580.8

 

      
                            IV CONCLUSION

In this Paper,
we presented the Performance comparison of Carry Skip adders designed using  Static CMOS technology by using 22nm Strained
Silicon CMOS technology. The effect of temperature on the Static Carry Skip
Adder is also analyzed by  Sweeping the
temperature from 27 (0C) to 107 (0C). The
Performance and analysis of 256-bit Conventional and Proposed Carry Skip Adder
is mentioned in the table. The Simulation results are obtained using HSPICE
software tool. It shows that as the temperature increases the delay of the
circuit also increases due to the reduction in actual power.

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